Lithoric — spot the bad optical chip before it ruins an AI chip

The bet we’re testing

Catch the bad chips early — before they cost you a full AI module.

Lithoric predicts how a photonic chip will behave after fabrication, after packaging, and in the real end application — by combining fab-calibrated device models with the thermal and mechanical physics of co-packaged optics, plus the link-level criteria that decide scrap vs ship (BER, FEC margin, eye opening, power budget, economics). Early factory tests alone can’t see that post-package tail; we model the chain so bad chips are flagged (or designs fixed) before they scrap a $10k AI module.

We care about getting photonic systems into the field — which means solving the reliability and manufacturing problems that kill ramps, not prettier simulation for its own sake.

The urgent problem

Today you can only tell if the optical chip is good after the whole module is assembled. Heat, mechanical stress, and heater budget in the package create failure modes wafer tests never see, and “good enough” depends on the assembly flow and the end link it must survive. By then it’s too late: a bad optical chip scraps the entire module, including the $10,000 AI chip next to it. The industry agrees this testing is slow, manual, too costly at scale — and there is still no standard way to catch those failures early.

Why now

CPO volume production begins in 2026 and scales fast through 2027–2028 — into the millions of light-based links a year, on track for tens of millions. Heat and packaging stress hit hardest exactly then. The industry calls this the make-or-break testing gap for that ramp; whoever sets a workable standard owns the window that is open right now.

Why our margins grow as the market grows

Lithoric is a software workflow: physics-informed prediction models that simulate post-assembly and end-use yield outcomes, economics-aware guardbands, and a design-iteration feedback loop. Customers start from Lithoric’s own databases of real environmental and fab-aware data — then refine those same physics models with their own fab measurements, or with field survival outcomes linked to the exact environments the hardware saw. That ingest can be automated, so friction stays low and the workflow stays pointed at one job: a reliable, manufacturable design with high yield. Because the product is software, value scales with CPO volume without proportional CapEx — and smaller design houses and startups get the same path without standing up a full multiphysics and yield org.

The technology

An AI robustness layer for silicon photonics.

Lithoric builds GPU-accelerated, physics-trained surrogate models and structured databases of manufacturing, packaging, assembly, and end-use environments — so predictions match the chip as built, the module as assembled, and the link as operated.

The challenges today

The tools exist; the workflow doesn’t. Simulation, wafer test, packaging FEM, and link analysis live in separate silos. Chaining them into a scrap-vs-ship decision is slow, manual, and out of reach for teams without a full multiphysics and yield org.
Simulation doesn’t match silicon. Nanometer fabrication variation, heat and mechanical stress make designs that are perfect in simulation drift or fail in the real fab and field.
Physics solvers are too slow. Classical electromagnetic and multiphysics simulation cannot explore the full process-and-temperature variation space.
The fab is a black box. Foundries withhold the as-fabricated geometry, so designers can’t test new designs against real process variability.
Wafer tests miss the package cliff. There is no standard method to combine early fab measurements with assembly physics and end-application criteria (link survival, BER/FEC, eye opening, power and cost budgets) — so good and bad chips are only separated after they’re expensively co-packaged.
Process and design IP can’t be pooled. Foundries and design houses will not put proprietary process or layout data into a shared model — any useful tool has to keep customer refinements isolated.

How we solve it

We train physics-ML surrogate models — neural operators (FNO), physics-informed neural networks and graph neural networks — that predict photonic device behavior across the full variation space in milliseconds instead of hours: mechanical stress, thermo-optic coupling, thermal crosstalk, heater budget, and aging. Fab measurements calibrate the manufacturing model (design → as-built geometry → measured performance). Package, assembly and end-system physics then explain the post-wafer failure tail that wafer tests alone cannot see. Every prediction carries calibrated uncertainty so each decision is trustworthy.

Beside the physics engine sits a real-world database of packaging and assembly flows, manufacturing variation for the chips that get packaged, environmental and reliability envelopes (thermal sweeps, FIT-class duty cycles), and the economics of scrap vs ship. Customers refine those priors with their own lab, lot, or field data so the model matches their process and use case. Refined models stay customer-specific — design-house and foundry IP is not mixed across tenants. That isolation is not optional: the industry already treats shared fab and design data as high-friction, and tools that ignore it do not get past the NDA. Each customer’s models keep improving from prior lots and field outcomes — so screening gets sharper over time, without pooling their IP.

Our first product sits on top of that stack: a calibrated accept/reject and optimized test guardband against the customer’s module and link criteria — so a bad optical chip is caught before it scraps the expensive AI chip beside it — and the same engine feeds redesign for yield when the failure is systematic.

Built on NVIDIA

Lithoric is designed around the NVIDIA accelerated-computing stack. We plan to build our surrogate models with NVIDIA PhysicsNeMo, train them on NVIDIA GPUs and DGX Cloud, serve them as NIM inference endpoints inside the design-and-test loop, and use Omniverse digital twins to fuse simulation with live fab data.

If even a third of these late failures can be caught before assembly — by modeling fab variation, package physics, and the real end link — this is a big new market. That’s the bet we’re testing right now — and we’d rather be proven wrong fast than find out too late.

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